1. Field of the Invention
The present invention relates generally to a semiconductor device having a memory function, a logic function and various functions specific to semiconductor materials, and a fabrication process thereof. More specifically, the invention relates to a multilayer interconnection structure of such semiconductor device and a fabrication process thereof.
2. Description of the Related Art
In conjunction with the refinement and increase of package density of semiconductor integrated circuits in recent years, refinement and employment of multilayer wiring structures has also progressed rapidly. In a logic type semiconductor device, since shortening of a propagation delay of a signal is essential, reduction of the dielectric constant of an interlayer insulation layer is demanded. Therefore, it has been studied to introduce a fluorine containing gas using a high density plasma CVD (Chemical Vapor Deposition) device (HPD-CVD) to deposit SiOF (dielectric constant approximately equal to 3.3) as a low dielectric constant layer.
When the SiOF layer as the low dielectric constant layer is used, it becomes possible to satisfactorily fill the space between wirings even when this space is less than or equal to 0.25 m. It is not possible to fill such small spaces in the case of a Si oxide layer formed by a parallel plate plasma CVD method (PE-CVD method) using TEOS (tetraethoxy silane) or the like, which has been widely used conventionally, as a material gas.
On the other hand, in addition to the HDP-CVD method, there is a method for forming the SiOF layer by addition of an etching type gas containing fluorine upon forming the Si oxide layer by the foregoing parallel plate plasma CVD method (PE-CVD method) (for example, Japanese Unexamined Patent Publication (Kokai) No. Heisei 6-302593). Even in this method, since etching is progressed simultaneously with deposition of the layer, good burying ability can be achieved so that the SiOF layer can be buried even in a wiring interval which is smaller in comparison with Si oxide layer.
For good burying ability of SiOF in a widely used product having closely spaced wiring patterns, study has been made of a memory type device, such as a dynamic random access memory (DRAM).
As wiring of the semiconductor device, an Al alloy has been widely used. However, upon formation of Al wiring, TiN layer as an anti-reflection layer preventing surface reflection during lithography, is frequently formed. A structure where the SiOF layer is directly deposited on a wiring having the upper surface covered with TiN, is preferred in view of lowering of the dielectric constant. However, due to low bonding ability between TiN and the SiOF layer, a problem is encountered in that peeling is easily caused at the interface between the layers. While burying ability becomes higher at higher fluorine concentration in the SiOF layer, the problem of peeling becomes more significant at higher fluorine concentration in the SiOF layer.
Separately from the foregoing problem, in the SiOF layer having high fluorine concentration, fluorine may be dispersed during a process, such as heat treatment or the like, to possibly cause corrosion by reaction with Al type wiring. For the measure of this problem, there has been proposed a method to grow Si oxide layer before growth of the SiOF layer (for example, Japanese Unexamined Patent Publication No. Heisei 7-74245). Section of the prior art employing this method is shown in FIG. 6. On a BPSG layer 602 of a Si semiconductor substrate 601, a Si oxide layer 604 not added fluorine is formed in a thickness of 100 nm by a PE-CVD method, on an Al wiring 603, using TEOS and O2. By forming the SiOF layer 605 in a thickness of 500 nm is formed on Si oxide layer 604 using TEOS, O2 and NF3, interval between Al wiring is filled. In this method, diffusion of fluorine in the SiOF layer is prevented by Si oxide layer and bonding ability of the anti-reflection layer TiN and the SiOF layer can be improved.
However, by growth of Si oxide layer, overhang shape 606 is formed between the wiring as shown in FIG. 6 to cause difficulty in burying the SiOF layer in the fine wiring 607. Particularly, coverage is lowered in the narrow space portion less than or equal to 0.25 xcexcm to cause void 608 or so forth between the wiring to be a cause of degradation of reliability of the wiring. Also, due to double the layer structure of the Si oxide layer and the SiOF layer having a high relative dielectric constant, the dielectric constant becomes higher in comparison with a single SiOF layer.
The problems in the prior art is low reliability of wiring due to the possibility of corrosion of Al type wiring by fluorine diffusion and the occurrence of peeling in the interface with TiN when the SiOF layer is directly grown on a first wiring having TiN as the anti-reflection layer.
The reason is that a fluoride of Ti is formed on the surface of the TiN by the SiOF grown layer or fluorine in the SiOF layer. There is a low bonding ability between the fluoride and the SiOF layer, and furthermore, since the Al type wiring and plasma SiOF oxide layer are in direct contact, fluorine may be diffused by heat treatment or so forth to react with Al type substance.
The second problem is that when a Si oxide layer is formed below the SiOF layer, despite of the fact that the SiOF layer is used as an insulation layer, the burying ability to the narrow wiring space portion is not high. Furthermore, it is not possible to achieve satisfactory lowering of the dielectric constant as a whole of the insulation layer.
The reason is that Si oxide layer is deposited immediately before deposition of the SiOF layer. Coverage of Si oxide layer is not good and forms an overhang like configuration to lower the burying ability of the subsequently formed the SiOF layer within the wiring space portion, and by stacking with Si oxide layer having high relative dielectric constant, dielectric constant of the overall interlayer insulation layer cannot be lowered satisfactorily.
It is an object of the present invention to provide a semiconductor device which can improve bonding ability with a metal wiring, prevent corrosion of wiring, improve burying ability between fine wiring, achieve low dielectric constant in overall interlayer insulation layer and achieve speeding up of the device with making a capacity between wiring small.
According to one aspect of the present invention, a semiconductor device comprises:
wiring formed on a semiconductor substrate by etching;
an insulation layer serving as a mask for etching in formation of the wiring, the insulation layer being formed only on the surface above the wiring via an anti-reflection layer; and
a Si oxide layer containing fluorine and burying the anti-reflection layer and the insulation layer therein.
The insulation layer on the wiring may be an Si oxide layer or an Si nitride layer.
The anti-reflection layer on the wiring may be formed of a refractory metal or a compound thereof, such as any one of Ti, W, TiN and TiW or a laminated structure thereof. A major component of the wiring may be Al or Cu.
According to another aspect of the present invention, a fabrication process of a semiconductor device comprises:
a metal layer forming step of forming a metal layer to be a base of wiring on a semiconductor substrate;
an anti-reflection layer forming step of forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer;
an insulation layer forming step of forming an insulation layer on the anti-reflection layer;
an insulation layer patterning step of patterning the insulation layer;
a wiring patterning step of performing patterning of the wiring by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring; and
an SiOF layer burying step of burying the patterned wiring with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.
The insulation layer patterning step may comprise a step of performing patterning of the insulation layer with taking a photoresist as a mask, and a step of removing the photoresist. The anti-reflection layer can be patterned simultaneously with the insulation layer.
The insulation layer forming step may form the Si oxide layer or the Si nitride layer by way of sputtering or CVD method.
The anti-reflection layer forming step may deposit any one of Ti, W, TiN and TiW by way of sputtering or a plurality components selected among Ti, W, TiN and TiW by way of sputtering.
The metal layer forming step may deposit a metal containing Al as a major component, and the wiring patterning step is performed by dry etching with a gas under a condition where a tapered side wall is formed with being formed a protective layer on the side wall of the wiring metal by etching.
The SiOF burying step is performed by a plasma CVD method or a high density plasma CVD method. At this time, a silane type gas or tetraethyl orthosilicate (TEOS), a fluorine type gas or triethoxy fluorosilane (TEFS), and oxygen are taken as source gases. When fluorine type gas is used, at least one of CF4, C2F6, NF3, SiF4 is used.
The fluorine concentration in the SiOF layer is preferably higher than or equal to 5%.
In the present invention, on the semiconductor substrate formed with the transistors or so forth, the metal, for example Al alloy, to be the first wiring layer is sputtered. On the first wiring layer, TiN layer to serve as the anti-reflection layer upon lithography. Also on the anti-reflection layer, the Si Oxide layer is deposited by the sputtering method or the plasma CVD method. In order to form targeted shape of wiring, a photoresist is applied and the resist is patterned by a known lithographic process. With taking this photoresist as a mask, the Si oxide layer is etched. At this time, TiN layer may also be etched subsequently. As the etching gas, gas system of CHF3, CF4, Ar and so forth may be used. When this gas system is used, Si oxide later and the TiN as base layer therebelow are normally etched. However, the Al type metal is not etched to terminate etching on the surface of the Al type metal. By slightly modifying the gas system or mixture ratio, it is also possible to terminate etching at the surface of TiN.
Subsequently, with taking the patterned Si oxide layer as a mask, Al type metal wiring is etched. By introducing BCl3, Cl2, N2 type gas as the etching gas and by using the high density plasma source, such as ICP or so forth, etching is performed. In this step, the surface of the Si oxide layer is slightly etched simultaneously with etching of the Al type metal. The side wall protective layer consisted of Al, Si, O and N is formed on the side wall of the wiring. When this gas type is used, deposition amount of the side wall protective layer of the wiring becomes variable depending upon N2 amount. By variation of deposition amount, the taper angle of the side wall of the wiring can be varied. By the taper angle of the wiring, the burying property of the SiOF layer is significantly affected. By adjusting the taper angle with N2 amount, burying ability of the SiOF layer can be improved to make it possible to bury the fine interval between wiring to form no void.
Furthermore, the side wall protective layer also serves as a barrier preventing diffusion of fluorine in the SiOF layer. Immediately before deposition of the SiOF layer in this effect, it becomes unnecessary to deposit the Si oxide layer.
Therefore, high burying ability and the SiOF with low dielectric constant can be certainly formed.
According to the present invention, since Si oxide later is formed on the TiN wiring, the TiN layer and the plasma SiOF layer are not in direct contact. By this, good bonding ability of plasma SiOF oxide layer can be certainly provided on the wiring.